1. Field of the Invention
The present invention relates to semiconductor circuits including logic circuits. In particular, the present invention relates to a semiconductor circuit including a latch circuit in which occurrence of soft error is suppressed.
2. Description of the Related Art
It has been known that a rays generated upon collapsing of radioactive isotopes contained in packages or wires in LSI (large scale integration) semiconductor circuits, neutron radiation derived from cosmic rays, and so on produce electrical noise in the LSI semiconductor circuits to thereby cause the semiconductor circuits to malfunction. Such malfunction is called soft error as opposed to hard error caused by failures in hardware, such as semiconductor circuits. Thus, the soft error is different from the hard error in that the soft error causes a transient malfunction in which the operation can be resumed but the hard error causes a permanent damage to a specific portion of a circuit.
However, when a transient malfunction due to soft error is stored in a latch circuit included in an SLI semiconductor circuit, the malfunction due to the soft error can become a stationary error in the semiconductor circuit.
In this case, with advancements in high-integration and microfabrication technologies and reductions in charge capacities of storage nodes in latch circuits included in LSI semiconductor circuits, the probability that a soft error resulting from the generation of electrical noise becomes a stationary error increases. This is because electrical noise facilitates the inversion of the logic states of the storage nodes of the latch circuits and thus the frequency of occurrence of malfunction states increases.
Accordingly, it has been proposed in recent years that the soft error resistance of logic LSI circuits including latch circuits is increased. For example, a method has been proposed in which parity between signals output from a latch circuit is obtained to check an error and an instruction is retried to prevent an error. However, in the error preventing method, for example, since the circuitry is configured so as to obtain parity, the number of circuits and the area of the circuitry increase, which causes a reduction in the circuitry performance.
In addition, a semiconductor circuit has been proposed in which at least three dynamic latches are prepared and wires are connected so that an output of one dynamic latch also serves as inputs of the other two dynamic latches to form three independent feedback loops (e.g., Patent Document 1: Japanese Patent Application Publication No. 4-170792).
The arrangement, however, does not increase the soft error resistance of the dynamic latches included in the feedback loops. Thus, there is a problem in that a malfunction state due to soft error in the dynamic latches becomes stationary. Accordingly, there is a problem in that, when malfunction states due to soft errors in two dynamic latches become stationary at the same time, the malfunction due to the soft errors becomes a stationary error in the semiconductor circuit.
The arrangement also requires multiple dynamic latches in order to store one storage state. Thus, there is a problem in that the area occupied by logic circuits increases or the response speed of the circuits decreases.